1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a redundant memory circuit having less number of devices configuring the whole device and lower wiring density in the memory region.
2. Description of the Prior Art
A semiconductor memory device is a highly integrated device provided with a great number of memory cell array blocks, that is difficult to function normally if there is even only one defective memory cell within memory cell array blocks. Therefore, in semiconductor memory devices, optional defective lines or defective rows within the memory cell array blocks are replaced with redundant lines or redundant rows to make it function normally.
Recently, semiconductor memory devices are proposed that are made to function normally by replacing optional defective lines or defective rows in many memory cell array blocks with redundant lines or redundant rows provided independently from the memory cell array blocks, with the objective to raise the production yield of semiconductor memory devices by increasing the flexibility of replacement and raising the relief efficiency for defective memory cells.
A typical example of a conventional semiconductor memory device having redundant memory circuits for replacing by lines the memory cell lines of cell array blocks with is shown in FIG. 9. FIG. 9 is a block diagram of the circuit of a conventional semiconductor memory device.
As shown in FIG. 9, this semiconductor memory device 100 is provided with plurality (only four are shown in FIG. 9 for simplicity) of cell array blocks 10-0 to 10-3 in which memory cells are located as basic memory circuits in plurality of lines and plurality of rows, a block selector 2 with which to select one from the cell array blocks 10-0 to 10-3, a line predecoder 1 with which to designate a cell line to be selected from among the lines of the selected cell array blocks 10, and line decoders 40-0 to 40-3 with which to select and drive a cell line according to orders from the line predecoder 1.
The block selector 2 outputs block selection signals (BSL0 to BSL3) for selecting one of the cell array blocks 10-0 to 10-3 based on the two higher bits of the line address signal (XA) which is input to the semiconductor memory device 100.
The line predecoder 1 outputs predecoding signals (XDCS) for designating cell lines to be selected from the selected cell array blocks 10 by predecoding bit signals other than the higher two bits of the line address signals (XA).
Line decoders 40-0 to 40-3 are provided respectively corresponding to cell array blocks 10-0 to 10-3, and when the corresponding line decoder activation signals (XDCE0 to XDCE3) which are output from the array control circuit 3 described below are on the active level, select and drive cell lines designated by predecoding signals (XDCS) which are output from the line prdecoder 1 from the corresponding cell array block 10.
Also, as shown in FIG. 9, the semiconductor memory device 100, as a redundant memory circuit, is provided with plurality of redundant cell arrays 11-0 to 11-3 each comprised of one line amount of the redundant memory cell, plurality of replacement address program circuits 50-0 to 50-3 provided corresponding to the redundant cell arrays 11-0 to 11-3, a replacement judging circuit 52, a redundant line encoder 7, plurality of array control circuits 3-0 to 3-3 provided corresponding to the cell array blocks 10, and redundant line drivers 34-0 to 34-3.
When there are defective lines in the cell array blocks 10-0 to 10-3, the replacement address program circuits 50-0 to 50-3 will memorize line addresses corresponding to the defective lines, and output active level redundant line selection signals (XRD0 to XRD3) when the line address signal XA designates line addresses of the defective lines.
The replacement judging circuit 52 outputs active level replacement judging signal (XRDN) when there are active level signals in the redundant line selection signals (XRD0 to XRD3).
The redundant line encoder 7 is provided at a position close to the replacement address program circuits 50-0 to 50-3, and encodes redundant line selection signals XRD0 to XRD3 that are output from the replacement address program circuits 50-0 to 50-3 and outputs them as redundant line selection encode signals (RXDS)
The array control circuits 3-0 to 3-3 are provided respectively corresponding to line decoders 40-0 to 40-3 and redundant line decoders 34-0 to 34-3, and output active level line decoder activation signals (XDCE0 to XDCE3) and sense activation signals (SAE0 to SAE3) when the corresponding block selection signals (BSL0 to BSL3) are on the active level and the replacement judging signal (XRDN) is on the inactive level, namely when the situation is normal.
On the contrary when the replacement judging signal (XRDN) is on the active level, namely in redundancy, they switch the line decoder activation signals (XDCE0 to XDCE3) into inactive level as well as decode the redundant line selection encode signal RXDS, and then according to the results of decoding when the corresponding redundant line selection signals (XRD0 to XRD3) are on the active level, output active level redundant line selection signals (RXDE0 to RXDE3) and the sense activation signals (SAE0 to SAE3).
The redundant line drivers 34-0 to 34-3 are provided each corresponding to redundant cell arrays 11-0 to 11-3, and when the redundant line selection signals (RXDE0 to RXDE3) are on the active level, select and drive the corresponding redundant cell array 11.
Further, as shown in FIG. 9, the semiconductor memory device 100 has a row decoder 5 which selects one row of each of the cell array blocks 10-0 to 10-3 and the redundant cell arrays 11-0 to 11-3, as a common circuit of a basic memory circuit and a redundant memory circuit, and sense amplifier circuits 6-0 to 6-3 having a transfer gate.
The line decoder 5 selects one row of each of the cell array blocks 10-0 to 10-3 and the redundant cell arrays 11-0 to 11-3.
The sense amplifier circuits 6-0 to 6-3 having a transfer gate sense amplify the memory data of the memory cells where the selected lines and rows of corresponding cell array blocks 10-0 to 10-3 and redundant cell arrays 11-0 to 11-3 cross each other, and the memory data of redundant memory cells 11-0 to 11-3.
Particular examples of circuits of an array control circuit 3 for four cell array blocks 10-0 to 10-3, a line decoder 40, and a redundant line decoder 34 are shown in FIGS. 10, 11, and 12 respectively. FIG. 13 is a circuit diagram of a memory region, and the memory region shown in FIG. 13 is configured as having an array division number of 16 (selected by X.sub.9 to X.sub.12), 64 main word lines (MWL)/array (selected by X.sub.3 to X.sub.8), and 8 subword lines (SWL, redundant cell lines)/MWL (selected by X.sub.0 to X.sub.2).
The array control circuit 30 is configured with two array activation signal generating circuits each corresponding to two upper and lower cell array blocks 10, and two redundancy decode circuits.
As shown in FIG. 10, the array activation signal generation circuit is provided with a NAND gate (11) having input from two predecoding addresses for selecting main word lines (X.sub.j+2N X.sub.j+3N and X.sub.jT X.sub.j+1N, shown in FIG. 13 as X.sub.9N X.sub.10N and X.sub.11T X.sub.12N respectively), and a NOR gate (13) which receives the output of the NAND gate (11) and the output of an inverter (12) receiving input of redundancy judgement signals (XREDUNB) which is outputted from a replacement judging circuit 52, and outputs through the inverter 14 the BSELBm which is outputted from the NOR gate (13).
It is further provided with a NOR gate (15) having input both from the output from the NOR gate (14) and the output from the redundancy decoder circuit, and outputs array activation signals (XAEBm).
On the other hand, the redundancy decoder circuit is provided with a NAND gate (17) having two encode addresses (RX.sub.0, RX.sub.1) for selecting redundancy word lines inputted through respective inverters (16A, B), and a NOR gate (18) receiving the output of the NAND gate (17) and the XREDUNB.
As shown in FIG. 11, the normal word driver is provided with a NAND gate (21) having two predecode addresses (X.sub.j+2N X.sub.j+3N and X.sub.iNxj X.sub.j+1N, shown in FIG. 13 as X.sub.3N4N and X.sub.5N6N respectively) for selecting main word lines, a NOR gate (22) receiving the output from the NAND gate (21) and the BSELBm outputted from an array control circuit 30, and a buffer (23) comprised of a voltage converter using the output from the NOR gate (22) as its input, and drives the main word lines.
As shown in FIG. 12, the redundancy word driver is provided with a NAND gate (32) which inputs two encode addresses (RX.sub.0 and RX.sub.1) for selecting redundancy word lines through respective inverters (31A and B), an output of the NAND gate (32), a NOR gate (33) receiving the output from the NAND gate (32) and the XREDUNB outputted from a replacement judging circuit 52 as its input, and a voltage converter (34) receiving the output from the NOR gate (33) as its input, and selects and drives the redundancy word lines.
In FIGS. 10 to 13,
X.sub.0 to X.sub.2 : addresses for selecting subword lines PA1 X.sub.3 to X.sub.8 : addresses for selecting main word lines PA1 X.sub.j+2N X.sub.j+3N : predecode addresses for selecting main word lines PA1 X.sub.jT X.sub.j+1N : predecode addresses for selecting arrays PA1 (X.sub.9N10N to X.sub.11T12T in FIG. 13) PA1 XREDUNB: redundancy judging signals PA1 BSELBm: normal word driver activation signals PA1 XAEBm: array activation signals PA1 RX.sub.0, RX.sub.1, RX.sub.2 : encode addresses for selecting redundancy word lines (one from 8 is selected by 3 bits)
(XDCS in FIG. 9) PA2 (X.sub.3N4N to X.sub.7T8T in FIG. 13) PA2 (BSLm in FIG. 9) PA2 (replacement judging signals (XRDNm) in FIG. 9) PA2 (Normal: high, redundancy: low) PA2 (line decoder activation signals (XDCEm) in FIG. 9) PA2 (enable: low, disable: high) PA2 (SAEm in FIG. 9) PA2 (enable: low, disable: high) PA2 (RXDS from the redundancy line encoder in FIG. 9).
The array control circuit 3, the line decoder 40 and the redundant line decoder 34 shown in FIGS. 10 to 12 function as in the following manner in the normal (non-redundancy) and in the redundancy. Explanation of the following functions are based on FIG. 13.
In normal time
(1) Line addresses are taken in through activation signals from the outside of the semiconductor memory devise 100 (not shown).
(2) Predecode addresses (X.sub.3N4N, X.sub.5N6N, X.sub.7N8N, X.sub.9N10N, and X.sub.11N12N, (XDCS in FIG. 9) for selecting main word lines are generated by a line predecoder 1 shown in FIG. 9, based on internal line address signals (XA) of the semiconductor memory device 100. Here, if, for example, X.sub.3 and X.sub.4 are at "low" level, X.sub.3N4N will be at "high" level and X.sub.3T4N, X.sub.3N4T, and X.sub.3T4T are all at "low" level.
(3) As function is normal and the redundancy judging signals (XREDUNB) are at "high" level, one of the 16 arrays is selected by the predecode addresses (X.sub.9N10N to X.sub.11T12T) for selecting arrays (X.sub.9T10N and X.sub.11N12N are selected in FIG. 13).
(4) The array activation signals (XAEBm) become "low" level and enable. Because of this, precharging of bit lines will finish, and preparation for sense-up activation will be established (not shown). As BSELBm is at "low" level, the normal word driver is in the enable state.
(5) One of the 64 normal word drivers is selected by the predecode addresses (X.sub.3N4N to X.sub.7T8T) for selecting main word lines.
(6) Hereafter, although not shown in the figure, main word lines (MWL) are selected, sense-up is activated, and reading and writing of data and so on are conducted.
In redundancy time
(1) and (2) proceed as in the normal time.
(3) As function is redundancy and the redundancy judging signals (XREDUNB) are at "low" level (not shown), one of the 16 redundant line arrays 11 is selected by the encode addresses (RX.sub.0, RX.sub.1, and RX.sub.2) for selecting redundancy word lines which is outputted from the redundant line encoder. In FIG. 13 RX.sub.0 is at "low" level, RX.sub.1 is at "high" level, and RX.sub.2 is at "high" level. Here redundancy arrays other than the selected redundancy array are in disable state because XREDUNB is at "low" level.
(4) The array activation signals (XAEBm) are at "low" level and enable. Because of this, precharging of bit lines will finish, and preparation for sense-up activation will be established (not shown). And, as BSELBm is at "high" level, the normal word driver is in the disable state.
(5) One of the 8 redundancy word drivers is selected by the encode addresses (RX.sub.0, RX.sub.1, and RX.sub.2) for selecting redundancy word lines.
(6) Hereafter, although not shown in the figure, subword lines (RWL) are selected, sense-up is activated, and reading and writing of data and so on are conducted.